spkr wrote:
Hi! I assume that the Vsync interrupt isnt programmable, but only observable. I have a few broad questions with regards to the cpu and the vsync behaviour:
That assumption is correct.
spkr wrote:
Is it known how many cycles there are per vblank? I would guess around 150240, but I wonder if there is an exact number.
I don't think anyone has bothered to measure yet.
spkr wrote:
When the screen address bit is set though altering bit 7 of $18063 when is this effectuated? I wonder if its immediate, or if its at some fixed time or not.
The change seems to be immediate, like any change you do to the video register.
spkr wrote:
Does the system allow for NTSC ouput? (Switching to 60hz vblank) or is it fixed at 50hz. I assume not, but doesnt hurt to ask.
This seems to be dependant on the ULA version: Apparently, there is a version produced for the US market that ended up in all Samsung-made QLs(?), and has an additional, non-documented bit (6) in the video register that will switch from 50 to 60Hz mode.
spkr wrote:
How does the 8 bit data bus to the CPU compare to the more common 68000 databus. Cycletables for the 68000 cpu are known, Im wondering how much is known about the 68008.
Well, it's half the width
If you have a look into the Motorola 68008 manuals, the information is all there. Note that the QL's own ROM frequently makes use of timed tight loops to achieve sub-timer-resolution delays, especially in the network and microdrive code.
spkr wrote:
Lastly, what are common practices to measure CPU time, is there a reliable way to count vblanks to measure execution of code, or is the interrupt behaviour limited to be observable alone?
If you're referring to visual "load indications" like flipping the border colour in the vblank like the ZX Spectrum guys do - No, there is no such easy method.
When I'm really interested in cycle counts, I drop my code into the Easy68000 68k simulator and see what it counts there. (That hands you back 68000 cycle counts, though, and is not guaranteed to be accurate)