Still possible to get Minerva ROM

[martyn_hill]

Hi Stu!

Actually, the JED file for the marvellous Mk2 was made available by Tony F and I took that, decoded it back in to a source EQN then made it a bit more readable - please see attached.

I'll take a photo of my (much hacked) Mk2 board and add some comments over the next few days before posting again.

Martyn.

[Silvester]

That's interesting, thanks for posting it, never seen a MK2 up close but I have always suspected there is a 7430 lurking under the EPROM. It's the only way I could figure it out (ie. providing DECODE in EQN file).

I did a discrete version, replacing GAL function with 7451/7400/7474/74126 (which I suspect uses less current than greedy GAL). I also added a couple of AT24C512 chips on PCB to give 128K of EEPROM. A spare 7400 gate also provides simple SCL/SDA activity LED. The PCF8583 has been powered by CR2032 now for about 3 years

[Derek_Stewart]

Hi,

I have Minerva MkII that I was repairing broken pins on the Rom Socket.

But I decided to remove the complete Rom Socket and see if I could reverse engineer the PCB. As Tony Firshman sent all his Minerva Stuff into the Texas Black Hole...

Here are photos of the Minerva MkII PCB minus the ROM Socket.

[Ruptor]

As Tony Firshman sent all his Minerva Stuff into the Texas Black Hole...

What is that? I thought Texas was still around.

[Derek_Stewart]

As Tony Firshman sent all his Minerva Stuff into the Texas Black Hole...

What is that? I thought Texas was still around.

Sorry, my little joke about someone who lives in Texas, who seemed to receive all the surplus QL equipment.

[QViewStu]

Just to set the record straight that’s not me

Dave and I did laugh at the irony of two English guys with an interest in a little regarded Sinclair machine (present company excepted) washing up within a couple of miles of each other in a Texas suburb…Minerva truly has mystical powers…

[Pr0f]

so looking at those stripped circuit boards - the chip under the ROM was a 13 Input NAND gage - so presumably used to do the finer address decoding for the SDA / SCL of the I2C offering - the actual driving of those signals appears to be done in software within Minverva.

It might be handy to know which pins of the 74LS133 are connected to which address lines of the ROM socket, although the addresses within the ROM can be determined.

* Entry point needing no RAM at all
ii_raw
move.l a3,d3
lea $bfdc,a4
lea 1(a4),a5
lea 2(a4),a2
lea 3(a4),a3
cmp.l #'gold',$4000a hopefully, a magic test for the gold card
bne.s new_cmd if not a gc, we're operating ok

so that looks like Address register A4 is getting a value $bfdc - which is towards the top of RAM ($bfff is last addressed ROM location for bottom 48K). The GAL logic is looking at A0 and A1:

/SCL = /A14 * ROMOEH * /A5 * A4 * /A0 * DECODE
+ /ROMOEH * /SCL
+ /SCL * /DECODE
+ A14 * /SCL
+ /SCL * A5
+ /SCL * /A4
+ /A14 * ROMOEH * /A5 * A4 * /f13 * DECODE
SCL.oe = vcc

/SDA = vcc
SDA.oe = /f16

/f16 = /A14 * ROMOEH * /A5 * A4 * /A1 * DECODE
+ /ROMOEH * /f16
+ /f16 * /DECODE
+ A14 * /f16
+ A5 * /f16
+ /A4 * /f16
f16.oe = vcc

Notice how /SDA is actually set to VCC (true) and it is the decoding of F16 that operates the tristate for this output - so it's either active or floating, which explains the resistors on the Minerva board. An ingenious way to implement SDA so that the others I2C devices on the bus can drive this pin.

For reading - it looks like Data bus line 0 is being used:

/D0 = /SDA
D0.oe = /A14 * ROMOEH * /A5 * A4 * DECODE

[Silvester]

so looking at those stripped circuit boards - the chip under the ROM was a 13 Input NAND gage - so presumably used to do the finer address decoding for the SDA / SCL

Using a 7430 (8 input NAND) would have been enough, SGC allows direct access through to $BF80-BFFF. Here's something I wrote a few years back (for my own reference in case I forgot) if it's any help.

Code: Select all

Minerva MK2 hardware
~~~~~~~~~~~~~~~~~~~

                SDA __  __ SCL
                      ||
A4          $BFDC   1100
A5          $BFDD   1101
A2          $BFDE   1110
A3          $BFDF   1111

SCL is written by A0, SDA is written by A1
SDA is read into data bit 0 (whereas write is A1). Is SCL read on data bit 1 ?

SGC & GC provide access windows at 0000-0007 (false read for MHD) and 128 bytes
readable at BF80-BFFF (real read for I2C etc). Proven by logic probe on ROMOEH.

First use of RTC is in ss_ramt_asm to initialise and deal with D1 reboot value.

SGC/GC v2.49 copies OS 0000-BFFF to ram, this would upset I2C momentarily. When
Minerva reboots it would do another initialise of I2C.

Don't know other hardware that might use top 128 bytes of OS area.

JS rom BFE2-BFFF vectors and version string, this is referenced internally!

So I can only assume that any reads at $BF80-BFFF resort to slow read of OS
ROM (like ROMport $C000-FFFF), else JS ROM would fail to find vectors.

-----------------------------------------------------------
SGC uses timing loops CACHE_OFF:
                                  QL      GC      SGC cache_off
        moveq   #12,d0            8       4       3
wait    subq.l  #1,d0             12      8       3
        bne.s   wait              18/12   10/8    9/5     taken/not

target = 44cycles, 5.852uS  original Minerva

QL   32 + 30*(n-1) = 384c = 51uS        #1 = 32 + 12 (!) = 44 = 5.852
GC   20 + 18*(n-1) = 218c = 13.625uS    #5 = 20 + 18*4 = 94c = 5.75uS
SGC  11 + 12*(n-1) = 143c = 5.96uS

! 12 is assumed from following instruction

------------------------------------------------------------

Special byte: 1 1 G V D C 1 Q
                  | | | | | |___ quit
                  | | | | |
                  | | | | |_____ must be 1 else err_bp
                  | | | |
                  | | | |_______ SCL
                  | | |
                  | | |_________ SDA
                  | |
                  | |___________ 0 kill bus to free state SCL=1, SDA=1
                  |              1 assume bus valid
                  |
                  |_____________ 0 device group is parameter value
                                 1 device group is in register

V=0 D=0 C=0 is invalid

Finish command buffer with special byte $FF, or where bus is not being
released between calls $F3 keeping SCL and SDA low.

    I/O byte: 1 0 S R B P A 0
                  | | | | | |___ must be 0 else err_bp
                  | | | | |
                  | | | | |_____ send ACK if R=1 on last read
                  | | | |
                  | | | |_______ send STOP
                  | | |
                  | | |_________ 0 R=0 destination is register
                  | |            0 R=1 source is control
                  | |            1 source/destination is data buffer
                  | |
                  | |___________ 0 write
                  |              1 read
                  |
                  |_____________ send START


R=0 A=1      is invalid
R=1 P=1 A=1  is invalid

NB. There appears to be a bug in GC & SGC speed patch versions. If you give
10x11010 ie. read into data buffer with no-STOP sent and do ACK on last byte.
Then it will send STOP because B is misinterpreted.

Also Phil Borman's copy for SGC SMSQ does same.

[Silvester]

Just to set the record straight that’s not me

Dave and I did laugh at the irony of two English guys with an interest in a little regarded Sinclair machine (present company excepted) washing up within a couple of miles of each other in a Texas suburb…Minerva truly has mystical powers…

Ah, would that be the Texas suburb which is at the end of the QL rainbow, where I believe - perhaps it's just a myth - that such things as dozens of unused Aurora boards exist (with all the components - just waiting to be bought into the world).

[Derek_Stewart]

Hi,

As I mentioned earlier, I was redrawing the Minerva MkII PCB, from the original PCB I have, with a view to producing some more PCBs, do you think this is a good idea?