The Sinclair QL Forum

Wow, that sounds like a cool thing to have experienced, thanks for sharing.

Regarding the ROM port, so you did actually rewire the (one) unused pin on the QL motherboard for it to have R/W capability?

I'll have to dig out my project to be sure - but there was no QL re-wiring required - Stuart pointed out that out of the pins there were, some were not required (from an OS point of view) and could be utilised to make it R/W with a modification of the firmware - still allowing for traditional ROM devices to be used as part of an expansion.
I'm sure I'm not doing justice to the concept with my increasingly failing memory.

OK, without any rewiring there is only one way: define some area of 256 bytes to be the "write area", any read to this translates to a write on the device. There is an area big enough on normal QL operating systems at the end of the ROM, maybe that was meant in this case. Apparently Laurence Reeves left some space at the end of the Minerva ROM for some kind of hardware, too, though he didn't tell me exactly for what (my German Minerva versions are bigger and occupy most of this space).

And how did that work with the Miracle hard drive?

I have remembered that we were using some of the address lines for data - I think there were enough address pins/lines to be re-purposed.
I hope this helps - it was a long time ago (I will find my project eventually to explain the concept in a little more detail!)

If you halve the addressable area you can use the top address pin as a read/write pin. Writes simply add $2000 to the address. That makes read/write a simple software trick. It has the same effectiveness as using the 256 free bytes to read from method, but allows for less usable ROM space. On the interface side of the transaction, the former method is leaner as the circuitry will look more like a traditional expansion. The latter requires decoding a few bits of the address bus and latching the bottom 8 bits of the bus as the data. Not as portable to traditional expansion use.

Thank you Dave - that sounds very much like how I recall Stuart explaining the idea (halving the addressable area - the ability to Write being straightforward in software)
(I incorrectly said firmware in my earlier post, but it was definitely a project that didn't require any hard/firmware level changes - probably why I thought that it was so ingenious)

He was a very bright fellow. His use of a video signal as a DRAM refresh interval timer was sublime....

Dave wrote:He was a very bright fellow. His use of a video signal as a DRAM refresh interval timer was sublime....

I like things like that - understanding of the base platform, and the requirements of his extension - and not wasting extra silicon to provide something that's already there. Nasta's implementation of the three MAC CPLD's in Aurora also showed the same kind of attention to detail.

We get lazy with having so much more available in newer chips.