ICL OPD

[Pr0f]

Yes - I seem to remember there was a mod to change one of the LS chips from a 240 to a 241 or vice versa - which did the invert so you could use a "classic" QL monitor - that should be enough to push out video to the Pico device - and then the lack of a monitor is sorted

[stephen_usher]

Indeed, but that also means that it's incompatible with the OPD monitor in future. I always prefer external adapters rather than modifying the machine itself, especially as every time you desolder a chip and solder a socket it risks damaging the PCB.

[Pr0f]

The 'cut and pull' technique is good in that instance - cut the chip pins using a pair of sharp side cutters, then use fine tweezers to pull the pin out when the pad is heated - it destroys the chip - but for a 40p LS TTL chip, this is no big sacrifice and the fact you are only working on one pin greatly reduces the risk of lifting tracks or damages the through hold if it's double sided.

It would then be possible to put the socket on a piggy back board, and have the original chip variant in the socket and it's inverse on the piggy back board directly addressing the picoVGA - or even save on doing that and invert the logic within the Pico - and just mount a VGA socket on the back of the case...

[Pr0f]

I picked up a 4 port ROM cartridge with PSION - it's in 2 ROM chips, so I am assuming I may have the 2.5 version - I will upload the images when I get chance. I suspect the reduction in ROM chip count is what allows the 2 extra decode lines to be made from the PLD.

[Pr0f]

Latest version of the decoding pdf - corrections for pins 27/28/29 on ROM Slots.

So pin 27 is the ROM Slot enable - tied by resistor in the ROM module - this enables the PLA to decode the ROM slot - the OPD will then check the slot for a valid ROM header and if found - add it to the OS tables. Verified that both the 2 slot and 4 slot ROM packs have the same basic functionality.

The 2 slot PLA has /VPA on it - this is not present in the 4 slot pack. Is this looking at /VPA value to decode it being in interrupt space?

[Pr0f]

Another update to the decoding - ULA3 pins now fully deciphered.

[Pr0f]

And still a mistake - what I thought was an /OE pin on the 2K RAM is actually a 2nd /CE pin - so read and write are gated by FC2

[Pr0f]

I think this will be it for a while - updated the address map with more detail and some corrections. Tidied up the ULA3 table and made corrections

What the schematics call EXTINT is not EXTINT on the ZX8302 - which disappears off to the part of the board near the phone module - and is probably used to detect low battery, but rather replaces it's functionality for the ROM Slots / keyboard / Modem / Telephone and also speech chip possibly

[stephen_usher]

I've been having issues with my OPD not starting up and giving the 5 bar error, which according to this document is "SRAM fault"

This morning I traced the issue to /CE1 never going low. Chased the line way over to the left of the board to a transistor which inverted the input... which I then traced all the way back to just above the ZX8302 then to the rear of the board and... the power/video connector, specifically the "shutdown" pin. So the problem was in the monitor.

It turns out there was a bad connection on the "power good" signal from the PSU. From what I can determine the "shutdown" signal merely disables the SRAM, possibly to try to prevent corruption if the PSU isn't fully up to 5V? But they could just use a zener diode on the +5V rail for that.

Anyway, that fault fixed... new fault created, the keyboard isn't working fully now. *sigh*

P.S. Reseated the keyboard ribbon and the keyboard's OK again.

[Pr0f]

I've updated the Decoding notes - latest one attached - there a good few corrections and some further lines identified. The powerdown pin on the J3 connector on the main board is indeed used to gate CE2 on the SRAM along with controlling the power to the whole board.

Enjoy the latest updates - I've a power/supply and PICOVGA interface to build so I can get the unit I bought recently working.

Once I've given it the once over - it will be time to start making a few mods for further expansion.

ICL OPD worklist / modifications:

1) Power supply for base unit - needs +12V, +5V and -5V

3.1. J3 - POWER AND VIDEO

15 way miniature 'D' Plug on Motherboard



Pin Function
1 Earth (video)
2 Red
3 Green
4 Blue
5 Horiz. sync
6 Vert. Sync
7 Earth
8 -5 volts
9 Earth
10 Monitor power
11 +5 volts
12 +5 volts
13 +12 volts
14 Powerdown
15 Csync
Notes:
Hold Pin 14 (Powerdown) at +5 volts for operation.

Integrate QLPICOVGA device for VGA output

2) HOME BREW MODIFICATION OPTIONS

The following changes can be made:

6.1 Change IC34 from a 74LS240 to a 74LS244 to invert the video & sync. outputs from the main board to allow the use of a standard monitor
6.2 Connect TP3 to pin 15 of J3 (solder pad above Q7) to provide a composite sync. signal for a monitor

3) Solder 28 pin socket for mainboard ROM (lower OS ROM) - and copy contents of bottom 2 ROMS to 64K FLASH.

4) Replace Lithium backup battery

5) Modify CPU board:

Remove 74LS138 and 74LS30 - daughter board will be used to provide /DTACK and ROM Selects - plus A15 and A16 for 128K RAM

RAM - will be at address 0x80000 - 128K - needs daughter board - Supercap backup?

3 remaining ROM sockets will be A0000, B0000 and E8000/F0000 64K ROMS each - the 2 top OS roms in A0000, and giving 4 more ROM slots of 32K in each half of 2 64K ROMS

ICL Basic to go into one of the ROMS - needs adapting for ROM image.