a DIY home build project...
a DIY home build project...
Been toying with the idea of filling an empty bbql case, I know ideas to replace the original motherboard have been put forward before, but I think the take up or support for these was never strong.
I have decided to put together a project based on some parts I have, and with the following aims:
1) Compatible with SuperBasic, and trap/vector compatible with any other software that doesn't have timing expectations based on processor clock
2) Able to support most plug in expansion cards that stick to the mechanism described in the Technical Guide.
3) Faster and more reliable serial ports - using Philips SC26C92 DUART which is an improved version of the 68681
4) Keyboard matrix support and PS/2 keyboard and mouse support
5) QL sound and Network.
6) Support for Aurora video modes and hdmi/vga output - memory access to video RAM is interleaved 1:1 with CPU, so no apparent wait states
7) 4Mb RAM, and a faster clock rate (12.5 MHz), so the base unit should be quicker than a stock QL, by at least a factor of 2
8) No Microdrive support - only the RTC register and Video register are emulated from the original ZX8301/ZX8302
9) Serial, QL Network, keyboard and sound through propeller and 68901 chip
10) LAN / Floppy / IDE and USB peripherals (Vinculum VDIP32)
Phase 2
A plug in 68EC000 accelerator board with 4Mb RAM which can either be used in 8 bit mode to extend the original board to 8Mb, or used in 16 bit mode to give a 4Mb accelerated machine with 16 bit accesses for RAM and a processor clock of 25MHz - mode selected before power on / reset.
Phase 3
A plug in 68EC030 accelerator board with 16MB SIMM, and 40MHz clock.
This is an early days project - and I don't know how far I will get with it - but my intention is to make the plans available, as I go. I am doing it for me, and will fund the project myself, but there is potential useful side projects in the USB device and I will use the CP2200 for my LAN chip, as used in the Q68.
I have decided to put together a project based on some parts I have, and with the following aims:
1) Compatible with SuperBasic, and trap/vector compatible with any other software that doesn't have timing expectations based on processor clock
2) Able to support most plug in expansion cards that stick to the mechanism described in the Technical Guide.
3) Faster and more reliable serial ports - using Philips SC26C92 DUART which is an improved version of the 68681
4) Keyboard matrix support and PS/2 keyboard and mouse support
5) QL sound and Network.
6) Support for Aurora video modes and hdmi/vga output - memory access to video RAM is interleaved 1:1 with CPU, so no apparent wait states
7) 4Mb RAM, and a faster clock rate (12.5 MHz), so the base unit should be quicker than a stock QL, by at least a factor of 2
8) No Microdrive support - only the RTC register and Video register are emulated from the original ZX8301/ZX8302
9) Serial, QL Network, keyboard and sound through propeller and 68901 chip
10) LAN / Floppy / IDE and USB peripherals (Vinculum VDIP32)
Phase 2
A plug in 68EC000 accelerator board with 4Mb RAM which can either be used in 8 bit mode to extend the original board to 8Mb, or used in 16 bit mode to give a 4Mb accelerated machine with 16 bit accesses for RAM and a processor clock of 25MHz - mode selected before power on / reset.
Phase 3
A plug in 68EC030 accelerator board with 16MB SIMM, and 40MHz clock.
This is an early days project - and I don't know how far I will get with it - but my intention is to make the plans available, as I go. I am doing it for me, and will fund the project myself, but there is potential useful side projects in the USB device and I will use the CP2200 for my LAN chip, as used in the Q68.
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Re: a DIY home build project...
Sounds interesting. Good luck with it.
Cheers,
Norm.
Cheers,
Norm.
Why do they put lightning conductors on churches?
Author of Arduino Software Internals
Author of Arduino Interrupts
No longer on Twitter, find me on https://mastodon.scot/@NormanDunbar.
Author of Arduino Software Internals
Author of Arduino Interrupts
No longer on Twitter, find me on https://mastodon.scot/@NormanDunbar.
Re: a DIY home build project...
It could well be - and I am happy to share any ideas as they come.
My idea was to keep the QL 8 bit internally, so use the 68008 chip with the 2 extra address lines. Some tests show that even the 8Mhz 68008 part can run at 12MHz, so the 10MHz part should run happily at 12.5MHz. A Xilinx CPLD will do all the address decoding and glue, and that would allow some nice tricks like shadowing ROM with RAM - making it technically possible to run SMSQ/E on the black box itself. It also means that address changes can be made simply by reprogramming the CPLD.
The hard part will be the graphics, as the idea is to use a FIFO to buffer accesses from the QL bus, and interleave these into the VRAM accesses - this means that the VRAM addresses can be accessed for write at any time with no waiting - even when driven at 40MHz. Read is always from QL main memory.
My IDE to SD card interfaces arrived yesterday - a perfect fit side by side in the lid of the QL case - shame it means they are upside down, but that makes connecting easier...
Hopefully post a picture tonight.
My idea was to keep the QL 8 bit internally, so use the 68008 chip with the 2 extra address lines. Some tests show that even the 8Mhz 68008 part can run at 12MHz, so the 10MHz part should run happily at 12.5MHz. A Xilinx CPLD will do all the address decoding and glue, and that would allow some nice tricks like shadowing ROM with RAM - making it technically possible to run SMSQ/E on the black box itself. It also means that address changes can be made simply by reprogramming the CPLD.
The hard part will be the graphics, as the idea is to use a FIFO to buffer accesses from the QL bus, and interleave these into the VRAM accesses - this means that the VRAM addresses can be accessed for write at any time with no waiting - even when driven at 40MHz. Read is always from QL main memory.
My IDE to SD card interfaces arrived yesterday - a perfect fit side by side in the lid of the QL case - shame it means they are upside down, but that makes connecting easier...
Hopefully post a picture tonight.
Re: a DIY home build project...
I have a few hundred 68EC030FE40 and about 80 68008FN10. Both good, both useful.
What do you make of the 68SEC000? I have one that runs at >40MHz without even getting warm. It can be configured as 8- or 16-bit data bus at power-on.
What do you make of the 68SEC000? I have one that runs at >40MHz without even getting warm. It can be configured as 8- or 16-bit data bus at power-on.
Re: a DIY home build project...
I think the 68(S)EC000 looks like a very useful chip. There is a CMOS RAM that also has configurable 8/16 bit mode, which is a very good match to this processor - Cypress CY62167E - I plan on using 2 of these.
With a latch and bi directional buffer, and a CPLD it should be possible to make something approximating to a gold card - but without the disk interface - because I will have that available on the board or through an extended rom port.
Having it switchable between 8 and 16 bit at power on / reset could allow the card to operate like a gold card but with potentially twice as much RAM and faster, or in 8 bit more, to insert itself into the middle of the memory map using the DMSCL or equivalent functional pin on the on board decode logic to disable the on board devices - so the lower 512K/2MB of RAM/ROM/IO would be in the QL, the next 4MB of RAM on the 68EC000 card, and the remaining half of the QL memory map at the top of the address map - for my design that would be the upper 2MB of RAM - giving an 8MB address space.
I have just ordered a 68EC030FE40 on Ebay - that wasn't you was it
If I have understood the 68000 range correctly, I can program for a device which is outside the physically addressable range of the chip, and it will echo throughout the memory map - both upwards, and down - so for instance the top 256K of the 128MB would also be the top 256K of 16MB and the top 256K or 4MB space - I will put my frame buffer there.
With a latch and bi directional buffer, and a CPLD it should be possible to make something approximating to a gold card - but without the disk interface - because I will have that available on the board or through an extended rom port.
Having it switchable between 8 and 16 bit at power on / reset could allow the card to operate like a gold card but with potentially twice as much RAM and faster, or in 8 bit more, to insert itself into the middle of the memory map using the DMSCL or equivalent functional pin on the on board decode logic to disable the on board devices - so the lower 512K/2MB of RAM/ROM/IO would be in the QL, the next 4MB of RAM on the 68EC000 card, and the remaining half of the QL memory map at the top of the address map - for my design that would be the upper 2MB of RAM - giving an 8MB address space.
I have just ordered a 68EC030FE40 on Ebay - that wasn't you was it
![Wink ;)](./images/smilies/icon_e_wink.gif)
If I have understood the 68000 range correctly, I can program for a device which is outside the physically addressable range of the chip, and it will echo throughout the memory map - both upwards, and down - so for instance the top 256K of the 128MB would also be the top 256K of 16MB and the top 256K or 4MB space - I will put my frame buffer there.
Re: a DIY home build project...
I don't sell mine. I bought them in bulk for super cheap a while ago from a trusted supplier in China. Every time I place an order, I bulk it op with 68EC030s to get the free express ship option. That way, they cost about $1.75 each. I added 40 to an order I placed earlier this week.
The Cypress SRAM is nice, and fairly affordable. The 5V friendly CY62167ELL-45ZXI gives no waits up to about 25 MHz. Nasta specced <=20nS for no waits at 40MHz.
The decoding behavior you're describing is usually a characteristic of incomplete address decoding.
I'm sure Nasta will pop up shortly.
The Cypress SRAM is nice, and fairly affordable. The 5V friendly CY62167ELL-45ZXI gives no waits up to about 25 MHz. Nasta specced <=20nS for no waits at 40MHz.
The decoding behavior you're describing is usually a characteristic of incomplete address decoding.
I'm sure Nasta will pop up shortly.
Re: a DIY home build project...
I probably haven't explained that all that well. If you load an Address register with say 0xFC000, and then address memory at that location on a 68008, it will not have the upper address lines, so will in fact address 0x0C000 - the last 256K of address space in an unexpanded QL - if a 68008FN chip with the A20 and A21 lines is used, it should place that at 0x3C000 - which would be the last 256K of 4MB. That works because the internal register is 32 bits still, but the upper bits are thrown away when the address is presented on the address bus.
It means I can write driver code for that address, but it will still work on the other memory layouts![Smile :-)](./images/smilies/icon_e_smile.gif)
I was looking at the timing for access on the bus - the 68000 has that 8 phase clock cycle - with each phase being one half wave of the cpu clock, so at 40MHz, they are going to be 12.5 ns each The DS line goes low at start of S3 and the data read in S7, so assuming 4 x 12.5ns for that, that gives 50ns - give or take a few ns for decoding. It will definitely work at 25MHz, and provided address decoding happens before S3 (address is available before), then DS strobing only the OE / WE it should work at 40MHz, with DTACK asserted early (DTACK grounded)
The complications for the Gold cards were having to slow things down for accesses to the QL peripherals and screen memory access, but if all the timing critical stuff is taken away, then it should be able to achieve a good speed improvement. I would replicate the copying ROM into RAM if it's in the 16 bit mode, as that would speed things up, but any accesses to the screen RAM would be to both 16 bit memory and vram if it was a write access, otherwise just from 16 bit memory.
It means I can write driver code for that address, but it will still work on the other memory layouts
![Smile :-)](./images/smilies/icon_e_smile.gif)
I was looking at the timing for access on the bus - the 68000 has that 8 phase clock cycle - with each phase being one half wave of the cpu clock, so at 40MHz, they are going to be 12.5 ns each The DS line goes low at start of S3 and the data read in S7, so assuming 4 x 12.5ns for that, that gives 50ns - give or take a few ns for decoding. It will definitely work at 25MHz, and provided address decoding happens before S3 (address is available before), then DS strobing only the OE / WE it should work at 40MHz, with DTACK asserted early (DTACK grounded)
The complications for the Gold cards were having to slow things down for accesses to the QL peripherals and screen memory access, but if all the timing critical stuff is taken away, then it should be able to achieve a good speed improvement. I would replicate the copying ROM into RAM if it's in the 16 bit mode, as that would speed things up, but any accesses to the screen RAM would be to both 16 bit memory and vram if it was a write access, otherwise just from 16 bit memory.
Re: a DIY home build project...
And 90% overlap with the Q68... just a matrix keyboard converter, and you're mostly done.Dave wrote:Sounds like our projects overlap 100%.
![Wink ;)](./images/smilies/icon_e_wink.gif)
Re: a DIY home build project...
I just like the idea of a black box QL full of goodies ![Smile :-)](./images/smilies/icon_e_smile.gif)
I also want to use it as a mule to try out new ideas...
I think like Dave I am more hardware oriented, but not above programming when I have to - just more of a plodder with that.
![Smile :-)](./images/smilies/icon_e_smile.gif)
I also want to use it as a mule to try out new ideas...
I think like Dave I am more hardware oriented, but not above programming when I have to - just more of a plodder with that.