I don't use FPGA with specific SERDES hardware, as they are expensive and not supported by free tools. The highest I tried was 0.8 Gbit/s per differential line by using the DRR_GENERIC block on ECP5. That requires a clock, so over an SATA cable, only half-duplex would be feasible.Brane2 wrote:SATA pair coudl do 600MB/s over that cable, which is more than enough to daisy chain whole apartment block with microdrives, floppies etc.
But I can't find simple parallel SERDES chip that I could use for the job.
Why not simply use UARTs with LVDS to connect your FPGAs? That should be okay up to 100 Mbit/s without specific hardware.
Price of the cable would be my very last concern, if it is fine technically. It will take another decade until SATA cables get problematic.Brane2 wrote:SATA is going to be obsoleted end get correspondingly more expensive.
You will have far more difficult challenges than cables. The first is to finish a major piece of QL hardware at all.