HAL equations / JED for use in a GAL chip

[Pr0f]

Has anyone programmed a GAL 16V8 with the JED code that was published (I think it's in the distribution and also on Dilwyns site too).

I noted the comment about using a slower GAL - got some on order - but was interested if anyone had done this and what was the result ?

[mk79]

[Pr0f]

Thanks Marcus - I am using a 'D' variant at 15ns - I have some 'A' variants at 25ns coming my way in the next few days - I will try again.

Symptoms with the D are a bit odd!

1488 chip got a bit warm - but it could be a bad one - running tests without that in place

Memory detected by Minerva on power up is only 64K, but sometimes it throws a memory error in the early 20000's memory range. So I may have some further RAM issues but I did solve one of these - missing address line on IC3

Haven't tested out ZX8302 access yet - that will be the biggy

I want to make sure this GAL isn't the source of any problems, since the other chips have all tested ok in another QL. Board is a T1 variant.

[tetroid]

Thanks Marcus - I am using a 'D' variant at 15ns - I have some 'A' variants at 25ns coming my way in the next few days - I will try again.

Symptoms with the D are a bit odd!

1488 chip got a bit warm - but it could be a bad one - running tests without that in place

Memory detected by Minerva on power up is only 64K, but sometimes it throws a memory error in the early 20000's memory range. So I may have some further RAM issues but I did solve one of these - missing address line on IC3

Haven't tested out ZX8302 access yet - that will be the biggy

I want to make sure this GAL isn't the source of any problems, since the other chips have all tested ok in another QL. Board is a T1 variant.

For Tx version you can use any PAL/GAL/ATF/PALCE with any speed.
You need to install C54 (47 pF ) capacitor.
For other QL PCB versions - capacitor 47 pF between pin 4 ( DSMCL ) of PAL chip and ground ).

[Pr0f]

Thank you Vitaliy,

Not sure what value I put in there - it was a low value - but I will make sure it is 47Pf. I also need to replace my reset switch as the original QL one I've used is not playing well, they are such a poor design. What switch part did you use in your design for the reset switch?

Dave.

[tetroid]

Thank you Vitaliy,

Not sure what value I put in there - it was a low value - but I will make sure it is 47Pf. I also need to replace my reset switch as the original QL one I've used is not playing well, they are such a poor design. What switch part did you use in your design for the reset switch?

Dave.

You need fo find :

DPDT Push Button Switch

For example :

https://www.ebay.co.uk/itm/2-Pole-Doubl ... 3251525219

https://www.ebay.co.uk/itm/5x-ITT-Schad ... 2242947964

[martyn_hill]

Hi Tetroid!

I was intrigued by your recommendation:

For other QL PCB versions - capacitor 47 pF between pin 4 ( DSMCL ) of PAL chip and ground ).

Out of interest, is the capcitor to effectively insert a delay before the GAL detects DSMC, or else just to reduce any noise causing it to falsely trigger at other times in the bus-cycle?

Regards.

[Pr0f]

Not sure - but with a 150pf capacitor in there it was quasi stable, with 47pf it is rock solid with repeatable results.

2nd back of memory was down to pin14 on the D1 RAM not being soldered - time for another eye test - but 2 joints out of a couple of hundred isn't bad.

ordered a new reset switch (different design) and some TVS diodes that will fit under the video 8 pin din connector.

I recompiled the GAL code from the equations with the device type set to 16V8A just for comparison - only the last bits are different:

Marcus compile (as device type 16V8)

L2128
1000000000000000110000000000000011000000110000001100000011000000*
L2192
11*
C2CFB*
0000

My compile today with it set to 16V8A:

L2128
1100000000000000110000000000000011000000110000001100000011000000*
L2192
11*
C2CFD*
0000

so that bit at L2129 is the ony differnce it seems.