Issue 6 VM12 & resistors confusion

[Ruptor]

I appreciate you taking the time to take the pictures. Yours doesn't have the 25nS pulse that on mine is regular and not part of the operation but I wonder if it is affecting things? Also is your OE pulse width 380nS =1/(2.631 MHz) because mine is 250nS significantly different? Strange that the rising edge of OE is so slow.
Oh! I just noticed 380nS is listed and I didn't have to work it out.

[Derek_Stewart]

Hi,

I was leading some old QL World Magazines, in QL World January 1993, Page 20

http://www.dilwyn.me.uk/mags/qluserworl ... 201993.pdf

Dennis Briggs, details a guide on testign the QL serial ports, which includes the resistors in question.

This maybe of some help.

[Ruptor]

We have moved on from the resistors but thanks for the article reference.
Took some more readings of the RAM problem and inconsistency that can be seen in the pictures. Usually the numbers screen is the thick horizontal white bars but for some reason the thin vertical bars occurred on the first to resets where the second reset was address 20004 instead of 20000. The third reset gave the usual white bars so still something inconsistent going on but a lot more rare. Here are the in and out RAM numbers for the three resets.

Reset thin vertical background lines
#20000
3B9C3B98
3B9D3B99
41AC3D12
40AD3D13
6E626E5A
6F636F5B
03322F0E
02332F0F
61B82C6E
61B92D6F
3B4E40B0
3B4F41B1
6E626E5A
6F636F5B
7A084EFA
7B094FFB
61C061C6
61C961C7
F0000000
F1010101
66F20105
67F30105
BE946618
BF956719
12284000
13294101
1E78F8F3
1F79F9F3

Reset thin vertical background lines
#20004
24214ED2
25214FD3
#20000
4A9C56CE
4B9D57CF

Reset normal background horizontal white bars
#20000
01056600
00056701
43EE9010
42EF9111
2E062C0C
2F072D0D
E0040200
E0050301
D60366EE
D70367EF
7FFC6700
7FFD6701

[martyn_hill]

Hi Ruptor

You'll have recognised this already from those sample results, but we clearly see that - aside from one pair of results (61C061C6 & 61C961C6) that may have been a typo, most pairs (94%) show bit-0 stuck at '1' when read-back, across 2, 3 or 4 of the 4 bytes tested. A few results (remaining 6%) show instead a '0' read-back when it should have been a '1'.

Whilst far from 100% authoritative, my guess at least is that bit-0 is picking-up noise from some where and not properly driven from the DRAM - pointing to any of:

a) a faulty DB Transceiver (LS245 - IC21) - pin 9 (more likely) or pin 11
b) a faulty DRAM IC (either or both of IC9 /IC1 - the two 64kB banks are connected in parallel, differentiated by CAS0 vs CAS1)
c) Poor connection/open-cct to any of the RAS, CAS or WE lines feeding those two specific DRAM ICs from the 8301 ULA.
d) Faulty 8301, affecting bit-0 on its DB0 pin 14.

Of course, as the RAM test never proceeds very far through the DRAM address range, we are only seeing results across a small sample of locations, which is where the actual displayed image itself could provide a more complete picture.

The fact that the displayed-image also shows those vertical white stripes suggests that the issue occurs 'inside' the 8301's private data-bus, so whilst not impossible, it seems unlikely that your custom EPROM mod is causing the issue - or if it is, it is in unison with a defective DB Transceiver that should otherwise segregate the two buses during the 8301 reading of the DRAM for display-image generation.

I beleve these latest results concur with MK's earlier analysis.

I don't see the TXOE/OE gated signal from the HAL being at fault here, even with that slow rise-time - we'd expect quite a different result if so.

Before replacing any further ICs, I'd check for (if you haven't already):
a) Good continuity between DB0 pin9 of IC21 and DRAM ICs 9 and 1 (pins 2 and 14 on each)
b) Good continuity to the RAS/CAS & WE lines feeding DRAM ICs 9 and 1 and equivalent pins on the 8301 (remembering CAS0->ICs 1-8 vs CAS1-> ICs 9-16.)

If these look OK, I'd next replace the DB transceiver - taking the opportunity to insert a DIL socket in the process. Only then replacing the DRAM ICs...

Good luck!
M.

[Ruptor]

Hi Martyn
Yes a typo where 61C061C6 should read 61C861C6.

a) a faulty DB Transceiver (LS245 - IC21) - pin 9 (more likely) or pin 11
If these look OK, I'd next replace the DB transceiver - taking the opportunity to insert a DIL socket in the process. Only then replacing the DRAM ICs...

I went through your list and have done the tests but in hind site some of the scope tests might not have been valid given they were done with other faults on the board like the dodgy 15 MHz clock and EPROM connection. The problem I have with looking at the EPROM side of IC21 is that it is under the veroboard. Then it hit me I can plug the home made EPROM in to the right hand ROM socket because the OE input is not used. Pin 11 is OK but pin 9 is stuck at an odd voltage right near the logic level so that explains why bit 0 is not always stuck. Why do you say "pin 9 (more likely)" is this a common problem? The strange thing is when the screen is updated with a new memory value pin 9 goes with logic signals so does that tell us which chip is faulty?

[martyn_hill]

Why do you say "pin 9 (more likely)" is this a common problem?

I said pin 9 was more likely just because this is the 'private-bus' side of the LS245 DB transceiver - i.e. the one connected to the DRAM/8301, rather than the CPU & ROM - and from what has been described so far, seems to be the side of the bus most likely to have the fault.

The strange thing is when the screen is updated with a new memory value pin 9 goes with logic signals so does that tell us which chip is faulty?

Pin 9 is DB0 (bit-0) on the private-bus, which connects to only DRAM ICs 1 and 9 plus the 8301 itself - as well as the DB Transceiver.

I'm not quite sure what you mean by "pin 9 goes with logic signals" - can you expand?

[mk79]

Then it hit me I can plug the home made EPROM in to the right hand ROM socket because the OE input is not used.

Um, what do you mean with "the OE input is not used"?

[Ruptor]

Pin 9 is DB0 (bit-0) on the private-bus, which connects to only DRAM ICs 1 and 9 plus the 8301 itself - as well as the DB Transceiver.
I'm not quite sure what you mean by "pin 9 goes with logic signals" - can you expand?

When Minerva updates the values on the screen every 10 seconds the line goes from about 1V to switching with data just like any other data line. I take this to mean that whatever writes to the display memory works but whatever reads doesn't see data and just gets zeros most of the time but because the level is around 1V a bit of noise particularly if the last data was a one causes the occasional 1 to come back. I guess that means it has to be the transceiver buffer driving pin 9 that is dead so nothing on pin 11 gets through.

Um, what do you mean with "the OE input is not used"?

Yes CE not OE the one that has different polarity for enabling the different ROM chips. I was just thinking enable when I typed it not really chip or output I mean nothing would work if it was OE.

[Ruptor]

Reluctantly started chopping the board up since it is pretty certain that IC21 is toast and here it is in pictures. I stuffed my fine cutters that I use for chopping the pins of surface mount chips just chopping one side as you can see because the pins on the driver were so tough. I chopped the other side using my tough old Lindstrom cutters & managed to unsolder the pins but solder sucking the holes was not so easy and that was when I thought the tracks were going to start flying. I used the wire poking through the hole technique to clear the rest. It was the tracks on the top layer that I was worried about the most but luckily all the tracks seem to be in place. There is no way I would be changing RAM chips to chase down a problem one chip is enough. I suppose I will have to bell out the tracks to check the vias are still connected but that can wait until tomorrow. Gone to put my feet up & have a beer to relieve the stress.

[martyn_hill]

Hi Ruptor!

That's quite a tidy job - anyone who's tried to remove ICs from an old board like the QL without lifting tracks or burning-out the vias will know only too well how delicate a job it can be!

Looking forward to hearing how things go tomorrow.

M.