8301 (ZX8301, the QL's Master Chip MC) - facts and figures

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mk79
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Re: 8301

Post by mk79 »

Nasta wrote:Yes, same here, but I remember tracing this (not sure... Samsung motherboard?) when I was designing Aurora. On it the 8301 is directly on the bus. Also, there is a GAL replacement of the HAL with equations, which also suggest the same thing.
One more follow up, Urs scanned an issue 6 board some time ago and it clearly has the ZX8302 connected to the ROM chips (viewtopic.php?f=12&t=2507&p=24558#p24552), so I presume that this isn't an upgrade by Samsung or whatever but that the Issue 6 schematic is generally wrong in this regard.

Cheers, Marcel


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Re: 8301

Post by Derek_Stewart »

NormanDunbar wrote:
By the way, thanks so much for your texts, this is pure nerd porn. I think I must collect them one day in one big volume
Or, on the QL Wiki? ;)
I have pasted all of Nasta's excellent information about the 8301 in LibreOffice along with the pictures. Which makes 33 pages of proof reading.

I will edit the document and include any other parts of the discussion and post here.


Regards,

Derek
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Re: 8301

Post by Nasta »

Peter wrote:
Nasta wrote: Have also a look at the maximum period required for /RAS. It does have a maximum (as long as it is) so it cannot be completely static. But I am sure at that rate the current consumption would be FAR lower.
Not sure what you mean - /RAS pulse width seems irrelevant, /RAS would never be active. Do you think there is a requirement to toggle /RAS if DRAM contents is never needed?
Most (though not all) 6164 family DRAM (and even to the latest parts) have (surprisingly) a limit to the maximum /RAS high spec (at least last time I looked). This suggests that it can't be completely statical. A long time ago i read the reason for this is that /RAS cycling is used to drive an internal charge pump which generates a negative substrate voltage for the RAM chip, which is not visible on the outside.
In all probability this should not mean anything since the RAM chips themselves would not be used, BUT address and data pins would still toggle levels. The problem might arise if the internals of the RAM chip expect that internal negative bias to operate the pin buffers properly, which is a big unknown. I suppose it could be tested for by looking at the data and address lines with all control signas (/RAS, /CAS, /WE) disabled and compare with the case of /RAS cycling at some very low speed (like a horizontal synch signal which has to be derived by the FPGA anywahy).
Peter wrote:
Nasta wrote: This suggests that you would implement the entire 128k inside the FPGA?
Not necessarily. If it was a PCB for BGA cases anyway, a small external RAM should also fit. But simply spending €4..5 more for 128 KB FPGA Blockram and save the extra work is tempting. Total overkill, I know.
I suppose depends on how the internal RAM is organized. An external SRAM (128k) is cheap and actually simplifies logic as it keeps the data lines to the FPGA input only, considering that internal block RAM needs only to be written (in parallel with the external 128k), while data is always read from the external RAM.
Peter wrote: Side remark: When Dave asked about the Q68 FPGA as a separate chip for re-use on other form factors, I was not totally opposed. I just asked for a separate discussion thread.
An interesting idea on many levels, but you are right, a separate thread is needed.

BTW regarding ROM shadowing, what would be the purpose? Ability to soft load different OSs?


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Re: 8301

Post by Nasta »

mk79 wrote:
Nasta wrote:BTW I do very much wish I had a comparable collection of data on the 8302. It would be nice to document it comprehensively all in one place.
I tried redacting your information into one coherent technical document, but at 16+ densely written A4 pages it was too much to handle right now Image
No hurry, it only took oh, some decades to get this info in the first place :)
On the other hand, I did not write this as a technical document, more like an article or a story because it seems to me it's more understandable that way. If it was down to the technical description, it would have been shorter and probably more organized. And with fewer spelling mistakes :)


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Re: 8301

Post by Peter »

Nasta wrote:A long time ago i read the reason for this is that /RAS cycling is used to drive an internal charge pump which generates a negative substrate voltage for the RAM chip, which is not visible on the outside.
I have seen a maximum /RAS high time only for similar DRAM chips yet, not the 4164 in particular. But there are certainly more datasheets than I randomly looked at.
I'm pretty sure the 4164 was built on homogenous substrate, at least the early ones. So if there was such a charge pump, pin buffers would indeed be affected as you suspect. (Still for a constantly deselected chip, I'd not expect more than a higher leakage current, if the substrate bias was missing.)
Nasta wrote:An external SRAM (128k) is cheap and actually simplifies logic as it keeps the data lines to the FPGA input only, considering that internal block RAM needs only to be written (in parallel with the external 128k), while data is always read from the external RAM.
Up to 128KB RAM, I'd probably prefer a simplified PCB over simplified logic. But this can be decided in detail if (and when) there is an actual design.
Nasta wrote:BTW regarding ROM shadowing, what would be the purpose? Ability to soft load different OSs?
Mainly to enable SMSQ/E, which needs to write ROM area at runtime.


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Re: 8301

Post by Nasta »

Peter wrote:
Nasta wrote: BTW regarding ROM shadowing, what would be the purpose? Ability to soft load different OSs?
Mainly to enable SMSQ/E, which needs to write ROM area at runtime.
Eh, yes - the thing is, we re limited to A16, A17 for decoding and that means 256k total which implies a cut-down version of SMSQ/E :(


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Re: 8301

Post by Peter »

Nasta wrote:Eh, yes - the thing is, we re limited to A16, A17 for decoding and that means 256k total which implies a cut-down version of SMSQ/E :(
I didn't mean that SMSQ/E must fit into a 8301 replacement - it would require a RAM extension anyway and could be loaded from mass storage under QDOS/Minerva.
But as you know, SMSQ/E must be able to (over-)write the ROM area (at least the first 4 KB or so) to work. Currently no QL extension offers this.


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Re: 8301

Post by QLvsJAGUAR »

Derek_Stewart wrote:I have pasted all of Nasta's excellent information about the 8301 in LibreOffice along with the pictures. Which makes 33 pages of proof reading.

I will edit the document and include any other parts of the discussion and post here.
Hi Derek,

did you complete this? A "book" called "ZX83 specific chips" covering the ZX8301, ZX8302 and 8049. Would be great!

I assume you take valued related Information out of other threads such as 8302 (viewtopic.php?f=2&t=2553) and 8302<>8049 communications (viewtopic.php?f=2&t=2299)...

Later this week, I may meet David Karlin again. David was the Chief Design Engineer leading the development of the Sinclair QL professional computer at Sinclair Research. Handing him over the document as a file may result in a review by him.

QL forever!
Urs


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Re: 8301

Post by Derek_Stewart »

Hi,

Here is the text in Word, ODF, PDF format.

I had to zip it up as the Forum software did not like .DOC or .ODF format files.

I also have produced KI-Cad Symbols for 8301 and 8302.

This was part of my KI-Cad QL circuit board Schematic update I will open a GitHub project for them.
Attachments
8301.zip
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Derek
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Re: 8301

Post by QLvsJAGUAR »

Derek_Stewart wrote:Here is the text in Word, ODF, PDF format.
Thank you!

I reworked it a bit, corrected some obvious spelling errors and added some fact & figures from other sources. Then I posted the document to David Karlin, let's see...


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