We've almost finished the design of the SSQB interface card, but got sidelined by working on the Issue 8, which is a rationalized QL motherboard. I have put an ESP-32S on it on the far right edge so the antenna is roughly where the 1377 used to be. Nasta believes this may cause some RF problems with the keyboard membrane. I say let's try it and measure the results to quantify the problem, if any.
The goal of the Issue 8 is to do a 'best version' of the QL with clean signals, and omitting the technologies we're leaving behind. Microdrives and UHF/composite video are gone. We have retained the QL net ports for now, because wifi/ethernet isn't actually working on this board yet, but once it is, they will likely go too. The board is heavily re-organized. I have placed the ESP board on the QL serial port 2, before the 1488/1489 using a simple TTL inverter/level shifter.
Bottom left to right 2x 512K SRAM, 64K EPROM, 8301 with 74HCT245 below, 2x 64kx4 DRAM, 8302. Above the SRAM is a 68008FN, above EPROM is a GAL20V8. Above the membrane connectors, sideways, is the 8049. The ESP-32S hangs off the right side of the board, so the antenna is out from under the metal keyboard plate.
Currently, all IO goes to that 2x20 connector at the back, which then goes to a 2-layer IO board which runs the entire IO length at the back of the QL. This saves around £15-20 per board. The IO board is long and thin, and costs little to make. The 4-layer CPU board is rectangular and optimal for manufacturing. If we didn't do it that way, production on the PCB would be around 3x the cost. The main idea behind this is that as we make improvements, you could replace the IO board or the CPU board. The IO board as currently planned: QL net x2, 9v barrel connector, RGB, 10/100 ethernet port, Ser1 d-sub, CTRL1 & 2 d-subs (German QL layout).
We've been held back for a long time by the QL's custom ICs. They suck.
The above all matters as it gives a context to our other decisions. For example, when we design a standalone ESP-32 wifi card, do we do it around existing serial (too slow!) around a common fast UART, or around the SuperIO UART we plan to use in future versions of the QL to replace... well.... almost everything. We have a couple of decisions to make there. I own a huge pile of SuperIO chips, the PC87307. They contain, conveniently: 2x 16550 UART (1.5mbaud) 1x parallel, 1x 8477 floppy controller as used on SGC, kbd/mouse controller, battery backed real time clock, power management, 16 GPIOs all in a handy dandy 160 pin QFP package!
I received an email last weekend complaining that we're being slow and wasting people's time. I'm sorry. What we're doing is complex, and the decisions we make will have a lasting impact. Also, it took 18 months for a team of 20+ people with massive resources to develop the QL. We're three people with few resources using very rusty memories and £50! We pretty much have one chance to do each step, no mis-steps, and we need to be well supported by purchases along the way because making things is expensive and we have to spend the money up front and then hope it sells. Emails like that disproportionately demoralize and demotivate me. They're far worse than sending requests for specific and limited help to people who are experts in a subject area and getting a no, or no reply at all.
Here's things we could use help with, if people want to pick up a nice little project for when the summer nights shorten and the air starts getting crisp:
- Configuring the 87307 SuperIO within the 64K from $10000-$1FFFF so each device appears at a rational address, is configured/configurable correctly eg: as to baud rate
- Using the ESP-32S or 87307 GPIOs to operate a keyboard membrane
- Using the ESP-32S bluetooth to operate a bluetooth keyboard and/or mouse
Your dev team: Nasta, Lau and me.