The Sinclair QL Forum

Hi Oliver Interesting! I can't readily decipher what that strip-board assembly is trying to accomplish, but the rest look like: a) EPROM converter board - I agree. Interesting approach to mounting (its quite tricky trying to mount right-ways up in the space available, so I can see why the inverted m...

Well, thanks Marcel! I have recompiled Minerva with the tiny change Marcel describes in his blog to the Scatter-load routine in mdvsc_asm and can confirm that LBYTES now works again on Min 1.98! Amazing bit of detective work - I am in admiration! It remains to be seen whether we should rev. Minerva ...

OOoOOooO!

I'm excited for your next installment, Marcel!

OK, no difference in behaviour with the SGC in my Iss5.

Looking more and more like the SGC ROM version...

Hi again When I test with LBYTEs in to a RESPR'd area, I get a crash but looking very different. The memory reserved was at 4064K, so well out of the contended DRAM range. This test repeatedly results in a very colourful vertical strip-pattern making its way steadily _up_ the display area. When I re...

Hi Martin I actually tested with both the IPC Interrupt enabled (default) and disabled (with that POKE!!53,128) - same result. Whilst I haven't yet tested other memory ranges for LBYTES, Marcel indicated that he had - again with the same result. I'll verify that later today, just to be sure. In any ...

My 11 yr old son will be gutted - one of his favourite activities is spotting Mr Lee in his various cameo roles in all the latest Marvel films...

RIP, Mr Lee!

Hi again Tobi and Martin All good points. Worth taking a step back for a moment. The simple fact that no one seems to have reported such an issue running Minerva (after v1.66 at least) on SGC (and possibly GC - according to Marcel's earlier findings) could be that its not such a common setup and per...

Now my head hurts! Having read the 68k PRM manual again and, as you point out Nasta, the use of not just the two usual USP and SSP, but instead one USP as well as independent Interrupt and Master SPs (ISP/MSP). It does seem possible that Minerva is only catering for a single (Supervisor) stack, wher...

Thanks Martin - it was good to re-read your older post and gives me some other ideas to consider. Meanwhile, I've burnt a fresh EPROM with Min 1.98 + Marcel's IO fix, but with the enable/disable interrupt instruction-pair in the MDV Scatter routine effectively removed (actually, replaced with 4x NOP...