The Sinclair QL Forum

I'm planning on making a similar mod - but replacing both logic chips on the right hand (processor) side of the PCB, and doing the same trick - three x 64K blocks - and the remaining socket switchable for either 128K ROM or RAM at the address designated for RAM expansion - for RAM to work - the code...

The other PCML disk interface had a 64180 CPU and ran CPM - so it may be a CPM format or derivative?

I pulled the lid off a ROM module, and pin 27 is just tied to ground. The resistor - value 2.7K goes from +5v to pin 1 of the Eprom, and the capacitor is tied between 0v and +5v. I think the same tying to ground would work perfectly well for the disk interface. I think the ICL OPD only decodes the /...

So I was looking at the circuit with a view to simplifying it. I am uncertain as to the purpose of the 74LS74 flip flops in the circuit - in the ROM modules, pin 27 is just simply grounded to indicate the presence of a device in the ROM slot - surely that could also be used here - saving a whole chi...

Derek_Stewart wrote: ↑Thu Jan 25, 2024 4:00 pm Hi,

Do not need a mouse interface, this is supplied on QIMSI.

Initially, I want some working Minerva MkII boards.

to be fair so is QL-SD equivalent provided by QIMSI

The original board was a little larger than the ROM socket footprint - having the RTC chip and GAL to accommodate. A straight copy would at least resurrect the I2C portion of Minerva. If the components were SMD - they should all fit into the same space, with the option of additional ROM images / I2C...

The main reason would be to isolate the I2C SCL and SDA pins if these are taken out to the outside world - giving protection against mishaps.

Is this to include the I2C components (clock and I2C output) ? If so could I suggest an I2C buffer chip be added ?

The SRAM chip does not need or use any signals from the 2 Sinclair ULA chips ZX8301/ZX8302 - it gets it's select signal from the ICL ULA, but this is gated with FC2 (high in supervisor mode) so that the RAM can only be accessed when Selected by address decoded by the ICL ULA and FC2 indicating Super...

The other one comes from the NAND gate - with FC2 and the CMOS RAM enable from the ICL ULA as the inputs to the gate - so the RAM can only be accessed in supervisor mode.