Issue 6 QL, Minerva (but that's irrelevant since you have to run SMSQ/E for SERnet), QIMSI and (non-Super) GC.
Maybe the SGC's 68020 has some influence?
Issue 6 QL, Minerva (but that's irrelevant since you have to run SMSQ/E for SERnet), QIMSI and (non-Super) GC.
I stand corrected, SERnet version 2.25 works with Minerva and my FIFO driver. The version that asked for SMSQ/E was 3.01, but I couldn't get that to work on QPC2 anyway.janbredenbeek wrote: ↑Tue Oct 17, 2023 11:22 amIssue 6 QL, Minerva (but that's irrelevant since you have to run SMSQ/E for SERnet), QIMSI and (non-Super) GC.
No photo here, but it's clearly identifyable in the QIMSI manual's photo.
Code: Select all
| QIMSI | PC/Q68 |
|-------|--------|
| 1 | 5 |
| 2 | 2 |
| 3 | 3 |
Thanks.Peter, Jan, ... thanks so much for that development. It is a very interesting complement to QIMSI.
Thanks. Some time ago I also wrote a program to configure baudrate settings etc. from QL side, that I didn't release due to lack of time.
From my ignorance, couldn't that have a solution with some "external protection"?janbredenbeek wrote: ↑Sun Feb 04, 2024 1:21 pm QIMSI's serial port has only minimal buffering so it's very likely that wrongly connecting pins 2 and 3 will fry your QIMSI, especially with PC ports which use 'real' RS-232 signal levels of +12 and -12 volts (unlike the Q68).
The QIMSI SER input is well protected already.afx wrote: ↑Tue Feb 06, 2024 8:17 pm Jan, Peter, thanks once again for the responses and support for this QIMSI feature.
From my ignorance, couldn't that have a solution with some "external protection"?janbredenbeek wrote: ↑Sun Feb 04, 2024 1:21 pm QIMSI's serial port has only minimal buffering so it's very likely that wrongly connecting pins 2 and 3 will fry your QIMSI, especially with PC ports which use 'real' RS-232 signal levels of +12 and -12 volts (unlike the Q68).