tofro wrote:SSS should be reasonably simple in case you have sufficient CPLD capacity and pins. It consists of an 8-bit port, an R2R ladder, a timer and an interrupt, maybe an OpAmp or a transistor in the simplest case.
The reason why it was so easy on Q40/Q60 came from the fast CPU speed, which
(A) allowed feeding the DAC registers with little time jitter
(B) did not slow down the whole system by the interrupt overhead
In this case, there would usually be only a 68008. So to achieve (A) you would at least need a second register level, not only the output register. For stereo, this means 2x2x8=32 Flipflops, which might already be 20...50% of all you got on an affordable 5V tolerant PLD. Those chips have relatively large combinatorial resources, but few flipflops.
(B) Looks almost impossible. Although a Q60 is over 100x faster than a QL, I vaguely remember the 20 kHz sound interrupt costs more than 1% CPU time. The 68008 would have little to no CPU time left. And the SSS data must come from somewhere...
The only solution I can see would be a hardware FIFO. Not necessarily as large as Q68.