ULA1 60Hz video - how much can I lift the clock ?

[Dave]

All US QLs have 50Hz output for video and 60Hz output for TV, but I don't know if this was done by changing the frequency or by changing the interrupt frequency.

Nice to see the device has some reasonable headroom.

[Nasta]

No they don't.
Absoultely the same frequency in all cases. The only difference is forcing the initial mode at power up and window size so things fit into the screen.
60Hz was indeed done, for US QLs. It was a small PCB with a TTL chip and some diodes glued onto the RAM array, shortening the vertical retrace period. Someone here posted a photo of it in a thread to do with either internal RAM or some problem with the machine. It would be nice to trace the circuit.

60Hz by using an 18M crystal will work, how long is anyone's guess but I'd say not a problem. More likely to work on the newer plastic case ZX8301 rather than the CLAxxxx ceramic version. The SPU will work at 9MHz and the ram also proportional to that, MDV, NET, SER will not work right. Supplying a 7.5MHz clock to the 8302 will restore serial operation, and possibly MDV but the faster CPU may still prevent proper working because some delays are implemented by software loops.

[Silvester]

The JSU rom controls the display depth through bit 6 of the master chip register at $18063 (0=625, 1=525 line). The photo shows a 74HCU04 (unbuffered hex inverters), probably doing nothing more than improving drive level and slew rate of crystal into ULA (the two upper wires are soldered onto the pcb tracks that lead from crystal to ULA).

[Silvester]

Poking 64 into $18063 on a UK QL doesn't do anything. I can only guess the US QL has a different ZX8301. IIRC the OPD (Tonto etc) used a ZX8301 variant clocked at 12MHz

Update: Looks like OPD used 15MHz for video, but ICL used ZX8301 at 12MHz for dram refresh on their 128K Memory Expansion Unit.

See: http://www.binarydinosaurs.co.uk/Museum ... riteup.php

[tofro]

Poking 64 into $18063 on a UK QL doesn't do anything. I can only guess the US QL has a different ZX8301. IIRC the OPD (Tonto etc) used a ZX8301 variant clocked at 12MHz

I don't think there were alternative ULA versions - I'd guess Sir Clive would rather have ripped someone's head off before actually paying for a different version. ASICs weren't exactly cheap to develop in those days....

The QL Technical Guide is somewhat unspecific on where the display control register is located (a Table says $18023, the text says $18063, probably due to incomplete address decoding) - Maybe $18023 does something? Don't have a QL with me to test at the moment.

Tobias

[Dave]

There might well be mask differences between CLA2310 and CLA2345. The CLA number is the mask/spin number, and the YB number is datecode/batch.

[belg4rion67]

The JSU rom controls the display depth through bit 6 of the master chip register at $18063 (0=625, 1=525 line). The photo shows a 74HCU04 (unbuffered hex inverters), probably doing nothing more than improving drive level and slew rate of crystal into ULA (the two upper wires are soldered onto the pcb tracks that lead from crystal to ULA).

I've found this note about sys variable at offset $32:

SV_TVMOD SYS_DTYP TV/Monitor mode.
0 = Monitor.
1 = PAL TV (SMSQ only).
2 = NTSC TV
<>2 = PAL TV (QDOS Only)

[Silvester]

The two loose ULA's I have are marked:

PS P B plastic
CLA2310
Y8453C

PS P 02 ceramic
CLA2310
Y8409J

On reset JS rom writes $00 to $18063, JSU writes $40

The only other place in the JS/JSU rom that $18063 is written to is in trap #1 call MT.DMODE

See references: QDOS SMS Reference Manual

page 65 section 12.1 Video explains use of 6x8 character set.
Page 73 section 13.6 SMS.DMOD D2=2
Page 173 sys_dtyp sysvar
page 190 mc_stat bits (b6 action missing)

BTW this might be of interest: http://en.inforapid.org/index.php?search=68K%2FOS
also http://www.theregister.co.uk/Print/2014 ... nclair_ql/