The Sinclair QL Forum

The device is very simple to use, but interfacing it to a QL is less so.

I am very willing to pair up with anyone who can design an AVR/PIC to do the parallel to serial conversion. That would change this from a "months" thing to a "weeks" thing. It needs at minimum to do 115,200 and preferably be capable of 2x, 4x, maybe 8x that.

Dave wrote:The device is very simple to use, but interfacing it to a QL is less so.

I am very willing to pair up with anyone who can design an AVR/PIC to do the parallel to serial conversion. That would change this from a "months" thing to a "weeks" thing. It needs at minimum to do 115,200 and preferably be capable of 2x, 4x, maybe 8x that.

Isn't a microcontroller overkill for this? UART is the ideal parallel to serial converter

Well, of course, but have you seen the prices and capabilities of UARTs these days? You're looking at $7+ for something 5V and with an upper limit slower than the QL with faster CPU is capable of. That statement is more about looking ahead than what is easy to do "right now."

It just so happens the serial port on my desktop's schematic capture right now uses a UART. It's just clunky, slow and expensive. But easier.

Will this help?
http://sif.itherm.cz/
It is serial interface for ZX Spectrum, dual UARTs (one for RS-232, second for WiFi or MIDI module).
Can it be modified for the QL?
"Device is based on two 16C650 Uarts with 7,3738MHz clock. By internal Baud rate generator is possible set speed from 50Baud to 460800Baud. SIF is completely powered by 3,3Volts by internal linear regulator, but all inputs are 5Volts tolerant."

That is a low power but fairly low speed device. Since we're looking to retire the 8302 and 8049 in the QL we're looking at something a little more capable. One option is the 16C554 which implements four serial ports up to 1500000 plus a parallel port. It's 16550 software compatible in terms of registers and etc. but in the PLCC package it has an Intel/Motorola pin which, if tied to ground, dramatically simplifies bus and control design.

That device, or something similar, would have 3-4x the peak throughput, and will be able to go on the journey with us to faster CPUs without having to be replaced later on.

It has 16 byte buffers which are enough to smooth things on the output side as the ESP-32 is VERY fast, but we will likely be using a 2048x9 FIFO on the input side so we do not have to poll it very often. That way it will not be a high maintenance item for the OS, sucking the joy out of everything else. The 2048kx9 FIFOs I snagged have a very useful half full flag. 2048 bytes sounds like a lot, but at full speed it could be completely filled in 0.0014 seconds. The FIFO would need to be serviced at least 1000 times a second even with that huge buffer to maintain throughput.

Initially it will probably be run at 500k or 800k for ESP-32, and have a limit of 262144 for plain serial. A limitation Nasta tells me is imposed by the limits of the 1488/1489 I have hundreds of in SIOC packaging.

I have 100 CP2200 ethernet controllers for sale super cheap if anyone wants them. Also a few wiznet 5300 devices. I think I will implement 10/100 ethernet via the ESP-32S, making access to it uniform - it's just like using wifi but no need to connect to an access point.

I prefer the solution of Dave