QL 34th Anniversary new hardware.

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Dave
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Re: QL 34th Anniversary new hardware.

Post by Dave »

Derek_Stewart wrote:Hi Dave,

A question regarding the memory mirroring, does this mirror the complete QL memory map or does it behave like the Gold Card?

The expansion looks great, I really like MInerva and doing without Multi-tasking Basic is some what limiting.
The only thing that's not mirrored is writes into video RAM and the QL IO area, for obvious reasons. ;)

My only regret is that we couldn't include Minerva on board due to size restrictions.


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Pr0f
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Re: QL 34th Anniversary new hardware.

Post by Pr0f »

Shame it couldn't go underneath the board as a slim flash package...


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Dave
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Re: QL 34th Anniversary new hardware.

Post by Dave »

Peter wrote:
Dave wrote:Yes, after this we do hope to produce a MUCH faster and more capable board. It would likely be based on the 68EC030 and a modern 5v tolerant FPGA.
A modern 5V tolerant FPGA would be fantastic for QL purposes. Any hint which FPGA family you mean?
The search continues. If you have any suggestions...


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Dave
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Re: QL 34th Anniversary new hardware.

Post by Dave »

Pr0f wrote:Shame it couldn't go underneath the board as a slim flash package...
Then how would people update it? You could program a flash in a QL, but you'd have to stop all multi-tasking...

I just decided it was easier to just give people a Minerva EPROM and adapter board free with purchase if they needed one. They're also available separately for £7 (standard Minerva/TKII image) or £8 (programmed with your custom ROM image.)
IMG_1884.jpg


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Re: QL 34th Anniversary new hardware.

Post by Whopper »

Dave wrote:
Peter wrote:
Dave wrote:Yes, after this we do hope to produce a MUCH faster and more capable board. It would likely be based on the 68EC030 and a modern 5v tolerant FPGA.
A modern 5V tolerant FPGA would be fantastic for QL purposes. Any hint which FPGA family you mean?
The search continues. If you have any suggestions...
Dave,

Have you thought about using bus switches? They would solve all of the voltage translations.


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Dave
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Re: QL 34th Anniversary new hardware.

Post by Dave »

There are a lot of 3v3 CPLDs and FPGAs that with a series resistor and internal clamping are 5v tolerant, and completely usable. I'm open to any of them. Especially ones that let you control slew rates - this would allow faster slew rates on the fast CPU/RAM side and slower slew rates on the QL side - a critical feature.

If it has enough internal capacity to also implement Aurora II (though, this would essentially be repeating Peter's work on video functionality - though widening that to 32-bit and removing the memory access bottleneck would be cool)....

The Altera/Intel Max 10 family are quite interesting...


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Re: QL 34th Anniversary new hardware.

Post by Whopper »

Dave wrote: ... The Altera/Intel Max 10 family are quite interesting...
Dave, perhaps the best method would be to build the VHDL / Verilog that you want, and the see which fpga it'll fit into. Then check the price.

When you come round, and get up off the floor, then you can chop bits out until you get a device that does what you want and can afford. :D


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Dave
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Re: QL 34th Anniversary new hardware.

Post by Dave »

I guess I see things differently. :D

For example, I am always willing to pay nearly double for a 4-layer PCB, when with a little extra effort a 2-layer PCB could be made to work. It increases routing flexibility, often helps signal quality, and it's nice to have proper power and ground planes. I think of going to 4-layer as just a component cost that's not even a big one. And it saves so much time during layout!

With this proposed future "super QL" the trick will be to offload as much of the vintage functionality as possible onto a single SuperIO device. This would require light OS/driver support if the SuperIO is chosen carefully so the constituent parts are mostly already used in a QL system already. For example, the PC87307 has the floppy controller used in the SGC, a standard DUART, standard PS2 keyboard/mouse, standard RTC.... This hugely reduces logic and pin costs on a CPLD or FPGA.

The sticky part is video. Peter could do the amazing job he did only because he kept the entire video and CPU section internal to the device. If he had to use external pins, it would have blown the budget.

If we look at the Q68 (and these comments are not questioning the business decisions or pricing of anyone involved with the Q68's production/sale) the price is £150. The component cost, rough estimate, is £25-30. If it used a double cost FPGA, would it really affect the final price that much? Most of the cost isn't in the parts, but in the development and actual manufacture labor. The components are only a tiny element of the final cost. The only way to lower the sale price is to buy components in bulk, to assemble in longer production runs and to sit on vast stocks for ages while they sell.

So yes, I'm 100% ready and willing to buy trays of expensive parts. And to use brute force approaches when the time and skill resources for more refined and efficient approaches just don't exist, meaning the project would take too long, be too costly or just never happen. It's a trap I've fallen into before. ;)


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Peter
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Re: QL 34th Anniversary new hardware.

Post by Peter »

Dave wrote:
Peter wrote:
Dave wrote:Yes, after this we do hope to produce a MUCH faster and more capable board. It would likely be based on the 68EC030 and a modern 5v tolerant FPGA.
A modern 5V tolerant FPGA would be fantastic for QL purposes. Any hint which FPGA family you mean?
The search continues. If you have any suggestions...
No, that's why I asked. It sounded like you knew a device.
Dave wrote:There are a lot of 3v3 CPLDs and FPGAs that with a series resistor and internal clamping are 5v tolerant, and completely usable.
Problem one: Only a fraction of the I/O pins usually has that feauture.
Problem two: A mass-grave of series resistors. In the end, level shifters are probably easier to solder.
Problem three: The required resistor values tend to be too large to provide sufficient drive current for all the pins inside the QL. This is because the clamp diodes are usually "weak", and the resistance must be large enough for the overshoot coming from the QL.
Dave wrote:Especially ones that let you control slew rates - this would allow faster slew rates on the fast CPU/RAM side and slower slew rates on the QL side - a critical feature.
Problem: "Slow slewrate" of a halfway modern FPGA is still fast compared to the QL.


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Re: QL 34th Anniversary new hardware.

Post by tofro »

Dave wrote: With this proposed future "super QL" the trick will be to offload as much of the vintage functionality as possible onto a single SuperIO device. This would require light OS/driver support if the SuperIO is chosen carefully so the constituent parts are mostly already used in a QL system already. For example, the PC87307 has the floppy controller used in the SGC, a standard DUART, standard PS2 keyboard/mouse, standard RTC.... This hugely reduces logic and pin costs on a CPLD or FPGA.
Once you start to think about putting sooo much legacy stuff in an improved manner to the left end of the expansion connector, I think it makes sense to forget about the right end of it and replace the legacy mainboard altogether. That would relieve you of any compatibility problems (except the keyboard matrix connectors, obviously :D ) You could even go for a full 3.3V implementation and wouldn't have to bother about component availability. Once you build a proper modern computer to the right end of the expansion port, you can also forget any legacy issues with regards to the expansion port itself...

Tobias


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