The Sinclair QL Forum

I would expect that CPMulator uses the ROM as either part of the code and/or look-up tables for Z80 emulation because the ROM slot access is about 1.8x faster than RAM where the code is normally loaded, which would be a big issue to get the emulation fast enough... I am not surprised it is not made ...

Hello everyone, Took some time to collect my thoughts - my journey to the meeting started very early Thursday, drove from my home to Nurmberg, then to Muhlheim and visited some friends that I have not seen for ages, slept over in Muhlheim then got to Dormagen on Friday afternoon. And from then on th...

An simple internal DIN41612 to ROMport connector board might be useful :idea: You may have noticed 2 x 2 extra pins in addition to the QL ROM port (the smaller ones near to the edge). One of them is leading QLNET and one is a "detection" pin. The other two could be used with such a connec...

Well, room reserved, so I hope to be there sometime early afternoon on Friday, and start back Sunday morning. It's going to be an interesting trip, Thursday Zagreb to Nurmberg to Frankfurt, then Friday morning Frankfurt to Dormagen. Then Sunday will be intense as I am driving back to Zagreb in one g...

With some luck I will be there!

The other approach is to control the clock going to the CPU - you can use a flip/flop or two within the FPGA to gate the clock signal to the CPU such that you get a 'glitchless' clock change - then you can select between a fast and slow clock. Any access to the ZX8302 can slow the CPU clock down if...

tofro wrote: ↑Tue Sep 05, 2023 9:15 pm

Peter wrote: ↑Tue Sep 05, 2023 2:07 pm so I didn't want to bother the whole forum at this point.

Don't worry.
They'll be fine.

And very interested

I think I solved it. I just delay 1 cycle bringing the DTACK low when PCENL is low and it now seems to work ok with 10Mhz cpu/ZX8301 clock and 7.5 Mhz ZX8302 clock. Just made the access cycle longer when talking to zx8302. This is the way to do it, and the way GC and SGC do it since their CPUs work...

If I am not mistaken the FPGA operates at 3.3V and I notice what seem like buffer chips to convert to 5V QL bus signals? If so, it might be a good idea to use a 68SEC000 chip on the 3.3V side coupled directly with the CPU and then convert signals that need to go to the QL bus to 5V. The chip has a s...

That being said you must not completely stop toggling RAS because it is used for the internal charge pump to negatively bias the substrate of the DRAM chips, without which the DRAM might consume too much current and not work right (a quirk of those older DRAM chips). Yes I forgot we discussed this ...