The Sinclair QL Forum

btw i think im also wiring the colors the csync & vsync and that VPAL to the "next" connector, but i dont think i need them on this extension.

thx a lot ! will read.. ... hm, that sounds very thrilling, but i have problems understanding why the extension should be in the address spaces mentioned -- until some unlucky person designs a peripheral that sits up at the address $FFFF5, which may generate /DTACK faster (so problems might occur). ...

hi martyn_hill, okay thank you, never heard of that, do you maybe have some pointer for more info ? does it also include DS(L) asserted ? would mean i need to wire FC0 & FC1 then to the CPLD (and sacrifice 2 of the "free" pins). i got some CUPL inspiration from a memory-expansion proje...

I suspect that Daniele was simply warning that your CPLD IO on Pin #43 should only ever go either Tri-state or High - never an active Low output.

ah ! yes, that makes sense. thank you !

thx for your input M68008, appreciate it but the technical manual says: "In peripheral cards which are to be added to the QL, it is necessary for each card to disable the circuitry on the QL itself when that peripheral card recognises its own address.This is achieved by pulling signal DSMCL hig...

if someone is interested, i'm adding the schematic for the next (v6) design, would be glad for some feedback. best & thx for replies so far
manfred

Yes, the PIC would be "memory mapped" from the QLs point of view, driver, 1 or 2 status bytes, the rest rx/tx buffer. i think it could work out with less address lines, like just 8, having a max of 256 bytes as ringbuffer for rx/tx then. But that doesn't leave any space for the driver then...

Thx for your questions Pr0f, The QLs address bus is directly connected to the PIC (well, A0-A13). The CPLD has A14-A19 (also directly, didn't make an issue so far). The PinManager UI gives me the following options, thats what i selected for these A0-A13: Analog: not selected Start High: not selected...

thx for you reply. wow, that says €6 per 5 pieces. i order them for ~7€ / piece ... nevertheless, redesigning to use buffers / transceivers for data + address lines. i'm not very sure if that is really coming from that 50cm cable, i had the same problem also with a previous version of the PCB that w...

Hi, I would need some advice regarding connecting a uC (PIC18F56Q83) to the expansion port, maybe someone here has experience with that. I have made a PCB with a CPLD (ATF1502 for addressing, DSL, DSMCL, DACKL, the SP lines) and a PIC together with some other chips like the databus is decoupled with...